1. Field of the Invention
The present invention relates to a floating gate based field programmable gate array (FPGA). More particularly, the present invention relates to floating gate based memory cells in an FPGA.
2. The Background Art
Programmable logic devices (PLDs) are integrated circuit devices which contain gates or other general-purpose cells whose interconnections can be configured by programming to implement nearly any desired combinatorial or sequential function. Field programmable gate arrays (FPGAs) are well known in the PLD art. FPGAs generally include an array of general-purpose logic circuits, typically referred to as logic blocks, which can be programmed by programmable elements to implement virtually any logic function. The programmed logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements.
It is well known in the art that both volatile and non-volatile programmable elements have been used to provide interconnection in FPGA devices. Volatile programmable elements are often a pass transistor controlled by a static random access memory (SRAM) cell. Nonvolatile programmable elements include antifuses and floating gate transistors. Programmable antifuse based architectures and reprogrammable SRAM and floating gate memory cell based architectures are well known in the FPGA art. In an SRAM based reprogrammable FPGA, the programmable elements are typically passgates controlled by information stored in an SRAM configuration memory. In an antifuse based FPGA, the antifuses are programmable elements that are formed by two conductors with a dielectric material sandwiched in between which represent an open state until programmed. The antifuses are disposed to provide the interconnections among the routing resources and to program the programmable logic elements.
In a floating gate transistor based FPGA, the floating gates are typically similar to those used in flash memories the operation of which is well known to those of ordinary skill in the art, but adapted for use in programmable arrays. Generally, in a floating gate transistor, an MOS based transistor has an additional unconnected or floating polysilicon layer disposed in a dielectric between a semiconductor surface and the gate of the MOS transistor. To program the floating gate transistor, electrons are placed on the floating polysilicon layer, and to erase the floating gate transistor, electrons are removed from the floating polysilicon layer. As is well known in the art, a floating gate transistor is programmed when sufficient electrons are placed on the floating polysilicon layer to provide a charge which prevents the floating gate transistor from being turned on by opposing the voltage applied to the gate of the floating gate transistor during normal operation that would typically turn on the floating gate transistor. When these electrons are removed, a normal operating voltage applied to the gate of floating gate transistor will result in current flowing through the floating gate transistor. During a read operation, this current may then be sensed to determine whether a particular floating gate memory cell has been programmed.
Proposed floating gate transistor memory elements employed in programmable logic devices include electrically programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), flash EEPROM. Ideally, a memory device optimizes density, preserves critical memory in a non-volatile condition, is easy to reprogram, and is read quickly. Flash memory is low-cost, high density, low power, and high reliability devices resulting in a high speed architecture.
FPGA architectures which employ floating gate devices as the storage elements in the memory cells have been proposed. In U.S. Pat. No. 5,812,450 to Sansbury et al., the floating gate based memory cells depicted in FIGS. 1A and 1B are proposed. A seen in FIGS. 1A and 1B, a pair of floating gate devices 10 and 20 are disposed in series between voltage sources 30 and 40. A common connection, described as a sensing node 50 may be employed to either drive a logic input or a switch somewhere on the device. FIG. 1B differs from FIG. 1A in that it includes a select transistor 60 that is disposed between the sensing node 50 and an erase node 70, and is used during the programming and erasure of floating gate devices 50 and 60.
In another known floating gate transistor based FPGA, the memory element of the memory cell employed to provide the interconnections among the routing resources and the programmable logic elements is also the switching element. Although there are some advantages associated with this approach there are also some drawbacks. Typically, as the size of the transistors in the logic change, the floating gate switch transistor does not scale that well with the change in the size of the logic devices. Further, employing a flash device as the switch often requires the switch to be larger in size than a typical flash memory element. As a result, a non-standard process for the larger than typical flash window is often used, and the resulting larger window may create reliability problems of charge retention and disturb of the stored charge during operation. It will be appreciated that weak storage elements are detrimental to the yield of good devices. Additionally, the switch properties are linked to the properties of the flash element. In a flash device, this creates a switch with high impedance, and also a switch that is sensitive to disturb.
There is therefore a need in the art to provide a floating gate based memory cell for a programmable logic device that includes a switch that scales with the logic devices in the programmable logic device, avoids the reliability problems of known floating gate memory switch cells, and does not link the switch in cell to the floating gate properties of the memory cell.